1. Field
The present teachings relate to dynamic systems and methods. In particular, the present teachings relate to dynamically biasing one or more field-effect transistors in order to control the drain-source voltages of each of the one or more field-effect transistors.
2. Description of Related Art
In low voltage (<4 volt) semiconductor technology such as silicon on insulator (SOI), typical transistors can only withstand a limited voltage across the drain-source terminals before experiencing reliability issues. A typical maximum voltage is around 4 volts for an SOI technology with a minimum feature size of 0.5 um for the gate electrode and decreases as the minimum feature size is decreased. This limitation poses a challenge when designing circuitry such as a DC-DC converter operating at a higher power supply voltage and producing an output signal that has a voltage swing matching the higher power supply voltage. The challenge lies in ensuring that each of the transistors in an output stage of the DC-DC converter are not overloaded beyond their operating limits. Such a situation may be encountered when a chain of transistors is powered by a high power supply voltage source and the voltage drops across each of the transistors turns out to be unequal, thereby leading to undesirable stress on one or more of these transistors. Various solutions have been provided to address this issue. In one prior art solution, a hard DC bias is used to place each of the transistors in a steady-state conduction state that is aimed at ensuring relatively equal voltage drops amongst the transistors.
FIG. 1 shows a prior art circuit 100 that incorporates such a hard DC bias arrangement applied to a cascode stack. The cascode stack is composed of PMOS transistors 125, 130 and 135 that form an upper leg 126; and NMOS transistors 145, 150 and 140 that form a lower leg 146. The upper and lower legs are connected to each other at a junction node 161 wherein a time-varying signal is generated when the cascode stack is in operation. The time-varying signal is propagated through a low pass filter composed of inductor 155 and capacitor 160 in order to create a DC output voltage at output node 162. A description directed at the upper leg 126 of the cascode stack will now be provided, and it can be understood that this description is equally pertinent to the lower leg 146 as well.
Transistor 125 is configured as a switching transistor with a suitable drive signal applied to a gate terminal of the transistor. The supply voltage V+ that is applied to upper leg 126 is significantly higher than the maximum allowable source-drain voltage (VDS) of transistor 125. Consequently, in order to maintain the VDS of transistor 125 at a safe operating voltage level, two additional transistors 130 and 135 are connected in series with transistor 125. The combination of the three transistors 125, 130 and 135 provide three VDS drops in upper leg 126, thereby ensuring that the VDS drop in transistor 125 does not exceed the maximum VDS of the device.
The VDS drops across each of transistors 130 and 135 is set to be relatively equal by providing a steady-state DC bias that is applied to each of the gate terminals of the two transistors. This steady-state DC bias is provided by fixed bias circuits 105 and 106 that output DC gate biasing voltages that place each of transistors 130 and 135 in conducting states with somewhat similar VDS drops. However, this biasing arrangement does not accommodate for variations in transistor geometries whereby the operating characteristics of transistors 130 and 135 are different thereby leading to unequal VDS drops in the two devices.
It is accordingly desirable to provide a biasing arrangement that ensures an even distribution of VDS voltage drops in the transistors of a cascode stack while preventing Vds electrical over-stress.